The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Jul. 17, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Da-Jun Lin, Kaohsiung, TW;

Bin-Siang Tsai, Changhua County, TW;

Ya-Jyuan Hung, Kaohsiung, TW;

Chin-Chia Yang, Tainan, TW;

Ting-An Chien, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 27/28 (2006.01); H01L 45/00 (2006.01); H01L 51/00 (2006.01); H01L 51/05 (2006.01); H01L 51/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/285 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/1675 (2013.01); H01L 51/0017 (2013.01); H01L 51/0048 (2013.01); H01L 51/0591 (2013.01); H01L 51/102 (2013.01);
Abstract

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.


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