The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2021
Filed:
Jul. 03, 2019
Dialog Semiconductor B.v., s-Hertogenbosch, NL;
Shou Cheng Eric Hu, Taichung, TW;
Jesus Mennen Belonio, Jr., Neubiberg, DE;
Dialog Semiconductor B.V., ‘s-Hertogenbosch, NL;
Abstract
A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.