The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Nov. 01, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaegwon Jang, Hwasung-si, KR;

Inwon O, Hwasung-si, KR;

Jongyoun Kim, Seoul, KR;

Seokhyun Lee, Hwaseong-si, KR;

Yeonho Jang, Hwasung-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/3121 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/13 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01);
Abstract

A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.


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