The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Mar. 09, 2020
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

International Business Machines Corporation, Yorktown Heights, NY (US);

Inventors:

Shay Reboh, Grenoble, FR;

Kangguo Cheng, Schenectady, NY (US);

Remi Coquand, Les Marches, FR;

Nicolas Loubet, Guilderland, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/10 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/76 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/2251 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/0847 (2013.01); H01L 29/10 (2013.01); H01L 29/1033 (2013.01); H01L 29/165 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/7613 (2013.01); H01L 29/775 (2013.01);
Abstract

A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.


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