The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Feb. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Victor Chiang Liang, Hsinchu, TW;

Chi-Feng Huang, Hsinchu County, TW;

Chia-Chung Chen, Keelung, TW;

Chun-Pei Wu, Nantou County, TW;

Fu-Huan Tsai, Kaohsiung, JP;

Chung-Hao Chu, Hsinchu, TW;

Chin-Nan Chang, Tainan, TW;

Ching-Yu Yang, Taichung, TW;

Ankush Chaudhary, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/0223 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 29/0847 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01); H01L 21/2822 (2013.01); H01L 21/823412 (2013.01);
Abstract

A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.


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