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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11088090 B1

PDFFull Text
Date of Patent:
Aug. 10, 2021

Filed:

Feb. 12, 2020

Package comprising a substrate that includes a stress buffer layer

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Sebastian Brunner, Deutschlandsberg, AT;

Kurt Wiesbauer, Deutschlandsberg, AT;

Horst Uwe Faulhaber, Tobelbad, AT;

Florian Rak, Deutschlandsberg, AT;

Andreas Haas, Deutschlandsberg, AT;

Franz Tinauer, Deutschlandsberg, AT;

Stefan Leitinger, Deutschlandsberg, AT;

Gerhard Fuchs, Deutschlandsberg, AT;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:

Qualcomm Incorporated

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 21/4763 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/532 (2006.01); H01L 21/56 (2006.01); H01L 23/28 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/28 (2013.01); H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 23/5329 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01);
Abstract

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, a buffer dielectric layer coupled to the at least one dielectric layer, and a buffer interconnect located at least in the buffer dielectric layer.

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