The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Jul. 22, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yao Yao, Albany, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Andrew Greene, Slingerlands, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/311 (2006.01); H01L 21/308 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66553 (2013.01); H01L 21/02532 (2013.01); H01L 21/3083 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/401 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/0262 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a plurality of first semiconductor layers alternately stacked with a plurality of second semiconductor layers on a semiconductor substrate, and laterally recessing the plurality of first semiconductor layers with respect to the plurality of second semiconductor layers to form a plurality of vacant areas on lateral sides of the plurality of first semiconductor layers. In the method, a plurality of first inner spacers are formed on the lateral sides of the plurality of first semiconductor layers in respective ones of the plurality of vacant areas, and a plurality of second inner spacers are formed on sides of the plurality of first inner spacers in the respective ones of the plurality of vacant areas. The method also includes laterally recessing the plurality of second semiconductor layers, and growing a plurality of source/drain regions from the plurality of second semiconductor layers.


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