The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Oct. 29, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Feng-Yi Chang, Tainan, TW;

Fu-Che Lee, Taichung, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/033 (2006.01); G03F 7/26 (2006.01); H01L 27/108 (2006.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0276 (2013.01); G03F 7/16 (2013.01); G03F 7/20 (2013.01); G03F 7/26 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 27/10823 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.


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