The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Aug. 21, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kevin G. Werhane, Kuna, ID (US);

Jason M. Johnson, Nampa, ID (US);

Yoshinori Fujiwara, Boise, ID (US);

Tyrel Z. Jensen, Meridian, ID (US);

Daniel S. Miller, Boise, ID (US);

David E. Jefferson, Meridian, ID (US);

Vivek Kotti, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 11/221 (2013.01); G11C 11/2253 (2013.01);
Abstract

Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.


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