The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Sep. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David W. Mendel, Sunnyvale, CA (US);

Jeffrey Erik Schulz, Milpitas, CA (US);

Keith Duwel, San Jose, CA (US);

Huy Ngo, San Jose, CA (US);

Jakob Raymond Jones, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); H03K 19/17736 (2020.01);
U.S. Cl.
CPC ...
H03M 9/00 (2013.01); G06F 1/12 (2013.01); G06F 13/4282 (2013.01); H03K 19/17744 (2013.01);
Abstract

A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.


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