The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Sep. 29, 2020
Applicants:

Global Unichip Corporation, Hsinchu, TW;

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Juh Kang, Hsinchu, TW;

Yu-Chu Chen, Hsinchu, TW;

Hsin-Han Han, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03M 1/08 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1028 (2013.01); H03M 1/0836 (2013.01); H03M 1/1023 (2013.01); H03M 1/121 (2013.01); H03M 1/1033 (2013.01);
Abstract

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.


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