The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Mar. 01, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Hang Chiu, Taichung, TW;

Chung-Chiang Wu, Taichung, TW;

Ching-Hwanq Su, Tainan, TW;

Da-Yuan Lee, Jhubei, TW;

Ji-Cheng Chen, Hsinchu, TW;

Kuan-Ting Liu, Hsinchu, TW;

Tai-Wei Hwang, Kinmen, TW;

Chung-Yi Su, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/088 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 29/51 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/32133 (2013.01); H01L 21/823456 (2013.01); H01L 27/088 (2013.01); H01L 29/517 (2013.01); H01L 21/82345 (2013.01);
Abstract

Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.


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