The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Mar. 30, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lakshmi N. Reddy, Mount Kisco, NY (US);

Gustavo Enrique Tellez, Essex Junction, VT (US);

Paul G. Villarrubia, Austin, TX (US);

Christopher Joseph Berry, Hudson, NY (US);

Michael Hemsley Wood, Wilmington, DE (US);

Robert A. Philhower, Valley Cottage, NY (US);

Gi-Joon Nam, Chappaqua, NY (US);

Jinwook Jung, White Plains, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.


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