The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Feb. 18, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhe Wang, Portland, OR (US);

Alaa R. Alameldeen, Hillsboro, OR (US);

Lidia Warnes, Roseville, CA (US);

Andy M. Rudoff, Boulder, CO (US);

Muthukumar P. Swaminathan, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 12/02 (2006.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/0207 (2013.01); G06F 12/0238 (2013.01); G06F 12/0893 (2013.01);
Abstract

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.


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