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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11069419 B1

PDFFull Text
Date of Patent:
Jul. 20, 2021

Filed:

Sep. 05, 2018

Test line letter for embedded non-volatile memory technology

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Jui-Tsung Lien, Hsinchu, TW;

Fang-Lan Chu, Taichung, TW;

Hong-Da Lin, Taipei, TW;

Wei Cheng Wu, Zhubei, TW;

Ku-Ning Chang, Taichung, TW;

Yu-Chen Wang, Huwei Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Eva Y Montalvo

Assistant Examiner:

David J Goodwin

Int. Cl.
CPC ...
H01L 29/788 (2006.01); G11C 29/02 (2006.01); H01L 21/28 (2006.01); G01R 31/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/544 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01); G11C 29/56 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G01R 31/2884 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/544 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); G11C 2029/5602 (2013.01); H01L 22/34 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54453 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

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