The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2021
Filed:
Jul. 25, 2019
Applicant:
Zhuhai Crystal Resonance Technologies Co., Ltd., Guangdong, CN;
Inventors:
Assignee:
Zhuhai Crystal Resonance Technologies Co., Ltd., Guangdong, CN;
Primary Examiner:
Int. Cl.
CPC ...
H03H 9/02 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 41/047 (2006.01); H01L 41/09 (2006.01); H01L 41/18 (2006.01); H03H 9/17 (2006.01);
U.S. Cl.
CPC ...
H03H 9/02015 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 24/94 (2013.01); H01L 41/0477 (2013.01); H01L 41/0973 (2013.01); H01L 41/183 (2013.01); H03H 9/174 (2013.01);
Abstract
A package for an electronic component wherein the package comprises a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; the active membrane being mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid, with filled through vias traversing the organic lid and walls for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a 'flip chip' configuration.