The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Apr. 03, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Baris Ozgul, Dundrum, IE;

Jan Langer, Chemnitz, DE;

Juan J. Noguera Serra, San Jose, CA (US);

Goran H. K. Bilski, Molndal, SE;

Richard L. Walke, Edinburgh, GB;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30098 (2013.01); G06F 9/30145 (2013.01); G06F 17/16 (2013.01);
Abstract

An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.


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