The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Oct. 02, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Heng Wu, Guilderland, NY (US);

Gen Tsutsui, Albany, NY (US);

Lan Yu, Voorheesville, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/823418 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/66666 (2013.01);
Abstract

A method for fabricating a vertical transistor device includes forming a plurality of fins on a substrate. The method further includes forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins. The method further includes selectively removing the interlevel dielectric layer between adjacent fins. The method further includes laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity exposing a bottom portion of each fin and extending beyond each fin. The method further includes epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.


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