The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2021
Filed:
Dec. 29, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Yi Xu, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/00 (2013.01); H01L 23/31 (2013.01); H01L 23/3107 (2013.01); H01L 24/02 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/42 (2013.01); H01L 24/97 (2013.01); H01L 25/065 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 24/13 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02319 (2013.01); H01L 2224/02321 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/06165 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/221 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/00014 (2013.01);
Abstract
Semiconductor packages including active die stacks, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes an active die having a top surface covered by a molding compound, and a bonding pad attached to only one interconnect wire. A method of fabricating the semiconductor package includes bridging a pair of dies stacks by the interconnect wire, and dividing the interconnect wire to form separate wire segments attached to respective die stacks.