The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Nov. 19, 2019
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Liyan Miao, Sunnyvale, CA (US);

Chentsau Ying, Cupertino, CA (US);

Xinhai Han, Santa Clara, CA (US);

Long Lin, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/00 (2006.01); H01L 21/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); C23C 16/40 (2006.01); C23C 16/52 (2006.01); C23C 16/34 (2006.01); C23C 16/24 (2006.01); C23C 16/452 (2006.01); H01J 37/32 (2006.01); C23C 16/54 (2006.01); H01L 21/683 (2006.01); C23C 16/455 (2006.01); C23C 16/509 (2006.01); H01L 21/677 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); C23C 16/24 (2013.01); C23C 16/345 (2013.01); C23C 16/401 (2013.01); C23C 16/452 (2013.01); C23C 16/45565 (2013.01); C23C 16/5096 (2013.01); C23C 16/52 (2013.01); C23C 16/54 (2013.01); H01J 37/32091 (2013.01); H01J 37/32165 (2013.01); H01J 37/32357 (2013.01); H01J 37/32449 (2013.01); H01J 37/32724 (2013.01); H01J 37/32733 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01); H01L 21/32055 (2013.01); H01L 21/6831 (2013.01); H01L 51/001 (2013.01); H01L 21/67109 (2013.01); H01L 21/67742 (2013.01); H01L 21/67766 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01);
Abstract

Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.


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