The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Feb. 21, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kerry Vander Kamp, Hillsboro, OR (US);

Jason Voelz, Lexington, SC (US);

James Goffena, Columbia, SC (US);

Robert Branch, Portland, OR (US);

Mahesh Natu, Folsom, CA (US);

Anand Enamandram, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 9/50 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0292 (2013.01); G06F 9/5005 (2013.01); G06F 12/0802 (2013.01); G06F 12/1441 (2013.01);
Abstract

Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.


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