Defect discovery and recipe optimization for inspection of three-dimensional semiconductor structures

Abstract

Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.