The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2021
Filed:
Dec. 08, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Chee Seng Leong, Gelugor, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/159 (2006.01); H03K 3/03 (2006.01); H03K 5/131 (2014.01); H03K 5/12 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/159 (2013.01); H03K 3/0315 (2013.01); H03K 5/12 (2013.01); H03K 5/131 (2013.01); H03K 3/0322 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00071 (2013.01);
Abstract
A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.