The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Oct. 02, 2019
Applicant:

Advantest Corporation, Tokyo, JP;

Inventors:

Ben Rogel-Favila, San Jose, CA (US);

Mei-Mei Su, Mountain View, CA (US);

John Frediani, San Jose, CA (US);

Shunji Tachibana, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31907 (2013.01); G01R 31/2844 (2013.01); G01R 31/3177 (2013.01); G01R 31/31703 (2013.01); G01R 31/31725 (2013.01); G01R 31/31908 (2013.01);
Abstract

The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.


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