The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Nov. 06, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Inventors:
Pei-Haw Tsao, Taichung, TW;
Chien-Jung Wang, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 21/56 (2013.01); H01L 24/02 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/1132 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/94 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/3512 (2013.01);
Abstract
A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.