The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Mar. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

George Chong Hean Ooi, Bayan Lepas, MY;

Lai Guan Tang, Tanjung Bungah, MY;

Chee Hak Teh, Bayan Lepas, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01); H01L 25/18 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H04L 12/861 (2013.01); G06F 30/34 (2020.01); G06F 115/08 (2020.01);
U.S. Cl.
CPC ...
G06F 13/20 (2013.01); G06F 30/34 (2020.01); H01L 23/538 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H04L 49/90 (2013.01); G06F 2115/08 (2020.01); H01L 2224/16225 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01);
Abstract

Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.


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