The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Dec. 16, 2019
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Chiao Tung University, Hsinchu, TW;

Inventors:

Tuo-Hung Hou, Hsinchu, TW;

Samuel C. Pan, Hsinchu, TW;

Pang-Shiuan Liu, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 29/47 (2006.01); H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 29/045 (2013.01); H01L 29/40117 (2019.08); H01L 29/41725 (2013.01); H01L 29/4234 (2013.01); H01L 29/47 (2013.01); H01L 29/66833 (2013.01); H01L 29/785 (2013.01); H01L 29/7839 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (D) material over the substrate. Source and drain contacts are formed partially over theD material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.


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