The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Jul. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Min-Shin Wu, Taipei, TW;

Meng-Sheng Chang, Chubei, TW;

Shao-Yu Chou, Chu Pei, TW;

Yao-Jen Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01); H01L 27/112 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract

An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.


Find Patent Forward Citations

Wu, Min-Shin. (2021). Anti-fuse device, circuit, methods, and layout (U.S. Patent No. 11031407). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11031407

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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