The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Jan. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Sung-Li Wang, Hsinchu County, TW;

Peng-Wei Chu, Hsinchu, TW;

Yasutoshi Okuno, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/02293 (2013.01); H01L 21/324 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method for manufacturing a semiconductor structure is provided. The method includes: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; introducing an agent onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited to the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. A semiconductor structure according to the method is also provided.


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