The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Aug. 19, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Shafqat Ahmed, San Jose, CA (US);

Khaled Hasnat, San Jose, CA (US);

Pranav Kalavade, San Jose, CA (US);

Krishna Parat, Palo Alto, CA (US);

Aaron Yip, Los Gatos, CA (US);

Mark A. Helm, Santa Cruz, CA (US);

Andrew Bicksler, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G06F 12/0804 (2016.01); G06F 13/28 (2006.01); G06F 12/0846 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/061 (2013.01); G06F 3/0653 (2013.01); G06F 3/0665 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G06F 12/0804 (2013.01); G06F 12/0846 (2013.01); G06F 13/28 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/224 (2013.01); G06F 2212/461 (2013.01); Y02D 10/00 (2018.01);
Abstract

Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.


Find Patent Forward Citations

Loading…