The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Oct. 01, 2018
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Seung Hoon Sung, Portland, OR (US);

Seiyon Kim, Portland, OR (US);

Kelin J. Kuhn, Aloha, OR (US);

Willy Rachmady, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); B41F 3/46 (2006.01); B41F 17/08 (2006.01); B41N 10/04 (2006.01); H01L 21/033 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); B41F 3/46 (2013.01); B41F 17/08 (2013.01); B41N 10/04 (2013.01); H01L 21/0332 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); B41N 2210/04 (2013.01); B41N 2210/14 (2013.01); Y10T 156/10 (2015.01);
Abstract

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.


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