The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Oct. 17, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Lung Tung, Kaohsiung, TW;

Min-Chang Liang, Zhu-Dong Town, TW;

Fang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); H01L 27/08 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 49/02 (2006.01); H01L 21/84 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 27/0802 (2013.01); H01L 27/1203 (2013.01); H01L 28/20 (2013.01); H01L 29/0646 (2013.01);
Abstract

A method performed by a computing system includes receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells and simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.


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