The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2021
Filed:
May. 18, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sameer S. Pradhan, Portland, OR (US);
Jeanne L. Luce, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/0234 (2013.01); H01L 21/02304 (2013.01); H01L 21/02323 (2013.01); H01L 21/02337 (2013.01); H01L 21/02356 (2013.01); H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7843 (2013.01); H01L 29/7848 (2013.01); H01L 21/02282 (2013.01); H01L 21/76834 (2013.01);
Abstract
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.