The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Aug. 05, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kohji Kanamori, Seongnam-si, KR;

Hyun Mog Park, Seoul, KR;

Yong Seok Kim, Suwon-si, KR;

Kyung Hwan Lee, Hwaseong-si, KR;

Jun Hee Lim, Seoul, KR;

Jee Hoon Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 2224/022 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/0903 (2013.01); H01L 2224/09181 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.


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