The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2021
Filed:
Apr. 24, 2019
Applicant:
Tongfu Microelectronics Co., Ltd., Nantong, CN;
Inventor:
Lei Shi, Nantong, CN;
Assignee:
TONGFU MICROELECTRONICS CO., LTD., Nantong, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/562 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/024 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/067 (2013.01); H01L 2924/0695 (2013.01); H01L 2924/07025 (2013.01); H01L 2924/3511 (2013.01);
Abstract
Packaging structure and method for forming a packaging structure are provided. A bonding layer is formed on the substrate. An improvement layer is formed on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are provided and include functional surfaces. The chips are mounted on the substrate by bonding the functional surfaces of the chips to the bonding layer through the openings. Top surfaces of the chips are lower than or flush with a top surface of the improvement layer.