The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2021
Filed:
May. 17, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Gracieli Posser, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Wen-Hao Liu, Cedar Park, TX (US);
Wing-Kai Chow, Austin, TX (US);
Zhuo Li, Austin, TX (US);
Derong Liu, Austin, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.