The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Jan. 16, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Hisada, Hachiouji, JP;

Toyohiro Aoki, Yokohama, JP;

Eiji Nakamura, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 27/0207 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.


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