The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Aug. 27, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Chiu-Hsiang Chen, Hsinchu County, TW;
Shih-Chun Huang, Hsinchu, TW;
Yung-Sung Yen, New Taipei, TW;
Ru-Gun Liu, Hsinchu County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 27/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); G06F 30/392 (2020.01); H01L 21/0274 (2013.01); H01L 21/308 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 27/0207 (2013.01); H01L 2223/54426 (2013.01);
Abstract
A method for fabricating a semiconductor device is provided. The method includes obtaining a pattern density of an integrated circuit (IC) design layout; adjusting a density of an alignment mark pattern of the IC design layout according to the pattern density; and patterning a material layer according to the IC design layout after adjusting the density of the alignment mark pattern.