The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Sep. 03, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Meng Zhao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0245 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/31111 (2013.01); H01L 29/0847 (2013.01); H01L 29/456 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/785 (2013.01); H01L 21/02645 (2013.01); H01L 21/26506 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.


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