The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Mar. 22, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Choonghyun Lee, Rensselaer, NY (US);

Brent A. Anderson, Jericho, VT (US);

Injo Ok, Loudonville, NY (US);

Soon-Cheon Seo, Glenmont, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 21/823842 (2013.01); H01L 21/823885 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.


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