The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Oct. 12, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chen-Yi Weng, New Taipei, TW;

Shih-Che Huang, Chiayi, TW;

Ching-Li Yang, Ping-Tung Hsien, TW;

Chih-Sheng Chang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/49838 (2013.01); H01L 23/5228 (2013.01); H01L 23/53214 (2013.01); H01L 23/5222 (2013.01); H01L 23/5329 (2013.01);
Abstract

A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.


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