The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Jan. 30, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Huai Huang, Saratoga, NY (US);

Takeshi Nogami, Schenectady, NY (US);

Alfred Grill, White Plains, NY (US);

Benjamin D. Briggs, Waterford, NY (US);

Nicholas A. Lanzillo, Troy, NY (US);

Christian Lavoie, Pleasantville, NY (US);

Devika Sil, Rensselaer, NY (US);

Prasad Bhosale, Albany, NY (US);

James Kelly, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76883 (2013.01); H01L 21/76802 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76864 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 23/53252 (2013.01); H01L 23/53276 (2013.01);
Abstract

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.


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