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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10977409 B1

PDFFull Text
Date of Patent:
Apr. 13, 2021

Filed:

Feb. 20, 2020

Apparatus and method of generating a layout for a semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ruey-Wen Chang, Hsinchu, TW;

Feng-Ming Chang, Hsinchu County, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

JCIPRNET

Primary Examiner:

Nghia M Doan

Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/392 (2020.01); H01L 27/02 (2006.01); H01L 29/786 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3323 (2020.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/1108 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.

Find Patent Forward Citations

Chang, Ruey-Wen. (2021). Apparatus and method of generating a layout for a semiconductor device (U.S. Patent No. 10977409). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10977409

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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