The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Jul. 02, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Guan Wang, San Jose, CA (US);

Qiang Tang, Cupertino, CA (US);

Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03K 3/017 (2006.01); H04L 25/06 (2006.01); H03K 5/156 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); H04L 7/00 (2006.01); H04L 25/02 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); G06F 1/04 (2013.01); G06F 1/10 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H03K 5/1565 (2013.01); H04L 7/00 (2013.01); H04L 25/0272 (2013.01); H04L 25/063 (2013.01);
Abstract

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.


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