The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Apr. 23, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yao-Ting Tsai, Taichung, TW;

Che-Fu Chuang, Taichung, TW;

Jung-Ho Chang, Taichung, TW;

Hsiu-Han Liao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H01L 21/31055 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/45 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01); H01L 29/66492 (2013.01); H01L 29/66515 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H01L 29/7883 (2013.01);
Abstract

Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.


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