The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Oct. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Yao Huang, Taipei, CA;

Wun-Jie Lin, Hsinchu, TW;

Chia-Wei Hsu, New Taipei, TW;

Yu-Ti Su, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/94 (2006.01); H01L 27/02 (2006.01); H01L 27/08 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 27/0262 (2013.01); H01L 27/0266 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/94 (2013.01); H01L 27/0811 (2013.01); H01L 29/861 (2013.01);
Abstract

A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.


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