The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Feb. 03, 2020
Applicant:

Sj Semiconductor (Jiangyin) Corporation, JiangYin, CN;

Inventors:

Yuedong Qiu, JiangYin, CN;

ChengChung Lin, JiangYin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 21/683 (2006.01); H01L 23/538 (2006.01); H01L 23/528 (2006.01); H01L 23/485 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/48 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/5389 (2013.01); H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.


Find Patent Forward Citations

Qiu, Yuedong. (2021). Packaging method and package structure of fan-out chip (U.S. Patent No. 10971467). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10971467

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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