The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Sep. 22, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shuo-Mao Chen, New Taipei, TW;

Der-Chyang Yeh, Hsin-Chu, TW;

Chiung-Han Yeh, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/568 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 2224/02233 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/03 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/0558 (2013.01); H01L 2224/05099 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13005 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/96 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/206 (2013.01);
Abstract

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.


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