The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Oct. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Zhang Qing, Shanghai, CN;

Jin Yi, Shanghai, CN;

Jiang Li, Shanghai, CN;

Ji Deng Feng, Shanghai, CN;

Liu Lu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/302 (2006.01); H01L 21/8234 (2006.01); H01L 21/304 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28079 (2013.01); H01L 21/302 (2013.01); H01L 21/304 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/76224 (2013.01); H01L 21/823437 (2013.01); H01L 21/823828 (2013.01);
Abstract

A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the polishing treatment includes: performing first polishing treatment using a metal polishing liquid; and performing second polishing treatment using deionized water. With the second polishing performance, the probability of forming a residue of the gate electrode material on the top surface of the interlayer dielectric layer is reduced, thereby improving device performance.


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