The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2021
Filed:
Jun. 17, 2020
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G06F 3/06 (2006.01); H01L 27/11573 (2017.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11551 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11578 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0688 (2013.01); G06F 3/0608 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11551 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11578 (2013.01);
Abstract
An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.